Set thread QoS to USER_INITIATED on Apple Silicon

[ssp3nc3r]

Summary

On Apple Silicon Macs, TBB worker threads are created with the default QoS class, which macOS may schedule to efficiency cores even when performance cores are available. This significantly degrades parallel performance.

This adds a pthread_set_qos_class_self_np() call in on_scheduler_entry() to set USER_INITIATED QoS, signaling to macOS that these are compute threads the user is waiting for. This causes macOS to prefer performance cores when available.

Details

• Adds #include <pthread.h> and #include <sys/qos.h> on Apple
• Calls pthread_set_qos_class_self_np(QOS_CLASS_USER_INITIATED, 0) when TBB worker threads enter the scheduler
• Only applies to Apple Silicon (__arm64__ or __aarch64__)
• No behavioral change on other platforms

Testing

Tested on macOS 26.2 (Tahoe) with Apple M3 Ultra (24 P-cores, 8 E-cores).

Before: CPU usage drops from ~800% to ~100-300% per chain after ~4 minutes (threads demoted to E-cores)
After: CPU usage remains stable on P-cores

Fixes #3277

[WardBrian]

Changes look good and relatively self contained to me, but I don't have a machine to test

@bob-carpenter is our resident Mac Silicon fan and has used some of this functionality recently, so maybe he can take a peek before we'd merge

[stan-buildbot]

---

Name	Old Result	New Result	Ratio	Performance change( 1 - new / old )
gp_regr/gp_regr.stan	0.09	0.09	0.99	-0.51% slower
gp_regr/gen_gp_data.stan	0.02	0.02	1.05	4.71% faster
arK/arK.stan	1.71	1.7	1.01	0.63% faster
eight_schools/eight_schools.stan	0.05	0.05	1.0	-0.49% slower
low_dim_gauss_mix_collapse/low_dim_gauss_mix_collapse.stan	8.34	8.3	1.01	0.52% faster
pkpd/one_comp_mm_elim_abs.stan	18.46	18.45	1.0	0.09% faster
pkpd/sim_one_comp_mm_elim_abs.stan	0.24	0.24	1.0	0.11% faster
sir/sir.stan	67.42	67.57	1.0	-0.24% slower
gp_pois_regr/gp_pois_regr.stan	2.73	2.7	1.01	1.08% faster
low_dim_gauss_mix/low_dim_gauss_mix.stan	2.56	2.56	1.0	-0.23% slower
irt_2pl/irt_2pl.stan	3.91	3.89	1.0	0.37% faster
arma/arma.stan	0.27	0.27	1.01	0.96% faster
garch/garch.stan	0.4	0.39	1.01	0.6% faster
low_dim_corr_gauss/low_dim_corr_gauss.stan	0.01	0.01	1.03	2.78% faster
performance.compilation	216.81	222.57	0.97	-2.65% slower
Mean result: 1.0054417050936904

---

Jenkins Console Log
Blue Ocean
Commit hash: 1b337025e3b7d081640d4cabb20b61b24aa7a46a

---

Machine information

No LSB modules are available. Distributor ID: Ubuntu Description: Ubuntu 20.04.3 LTS Release: 20.04 Codename: focal

CPU:
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
Address sizes: 46 bits physical, 48 bits virtual
CPU(s): 80
On-line CPU(s) list: 0-79
Thread(s) per core: 2
Core(s) per socket: 20
Socket(s): 2
NUMA node(s): 2
Vendor ID: GenuineIntel
CPU family: 6
Model: 85
Model name: Intel(R) Xeon(R) Gold 6148 CPU @ 2.40GHz
Stepping: 4
CPU MHz: 2400.000
CPU max MHz: 3700.0000
CPU min MHz: 1000.0000
BogoMIPS: 4800.00
Virtualization: VT-x
L1d cache: 1.3 MiB
L1i cache: 1.3 MiB
L2 cache: 40 MiB
L3 cache: 55 MiB
NUMA node0 CPU(s): 0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78
NUMA node1 CPU(s): 1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57,59,61,63,65,67,69,71,73,75,77,79
Vulnerability Gather data sampling: Mitigation; Microcode
Vulnerability Itlb multihit: KVM: Mitigation: VMX disabled
Vulnerability L1tf: Mitigation; PTE Inversion; VMX conditional cache flushes, SMT vulnerable
Vulnerability Mds: Mitigation; Clear CPU buffers; SMT vulnerable
Vulnerability Meltdown: Mitigation; PTI
Vulnerability Mmio stale data: Mitigation; Clear CPU buffers; SMT vulnerable
Vulnerability Reg file data sampling: Not affected
Vulnerability Retbleed: Mitigation; IBRS
Vulnerability Spec rstack overflow: Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl
Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2: Mitigation; IBRS; IBPB conditional; STIBP conditional; RSB filling; PBRSB-eIBRS Not affected; BHI Not affected
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Mitigation; Clear CPU buffers; SMT vulnerable
Vulnerability Vmscape: Mitigation; IBPB before exit to userspace
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb cat_l3 cdp_l3 invpcid_single pti intel_ppin ssbd mba ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm cqm mpx rdt_a avx512f avx512dq rdseed adx smap clflushopt clwb intel_pt avx512cd avx512bw avx512vl xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts hwp hwp_act_window hwp_epp hwp_pkg_req pku ospke md_clear flush_l1d arch_capabilities

G++:
g++ (Ubuntu 9.4.0-1ubuntu1~20.04) 9.4.0
Copyright (C) 2019 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Clang:
clang version 10.0.0-4ubuntu1
Target: x86_64-pc-linux-gnu
Thread model: posix
InstalledDir: /usr/bin

[SteveBronder]

Leaving this as is should be fine, but pthread_set_qos_class_self_np should work for x86 as well.

[bob-carpenter]

I only added those statements after @WardBrian or @SteveBronder told me about them. I haven't profiled without, which I should probably do. We ifdef-ed them so they would be no-ops other than on Apple OS.

[WardBrian]

@bob-carpenter you might have gotten lost in the notification soup, this is about adding similar settings to the Math library that you had previously set in walnuts

[bob-carpenter]

I may have wrongly assumed people reading this knew I was working on WALNUTS, but I understood the context here. @WardBrian pinged me and I was just responding that I haven't even verified that the commands do anything useful in the place where I am using them. You might want to ask @SteveBronder, who I believe is the one who recommended these commands for Apple Silicon where there are a combination of "performance" cores and "efficiency" cores.