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@lowRISC

lowRISC

Developing the Silicon Commons

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  1. opentitan opentitan Public

    OpenTitan: Open source silicon root of trust

    SystemVerilog 3.3k 975

  2. ibex ibex Public

    Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

    SystemVerilog 1.8k 707

  3. ibex-demo-system ibex-demo-system Public

    A demo system for Ibex including debug support and some peripherals

    C 93 74

Repositories

Showing 10 of 154 repositories
  • opentitan Public

    OpenTitan: Open source silicon root of trust

    lowRISC/opentitan’s past year of commit activity
    SystemVerilog 3,255 Apache-2.0 975 1,472 (11 issues need help) 386 Updated Mar 27, 2026
  • dvsim Public

    DVSim is a build and run system written in Python that runs a variety of EDA tool flows

    lowRISC/dvsim’s past year of commit activity
    Python 6 Apache-2.0 10 23 5 Updated Mar 27, 2026
  • mocha Public

    CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.

    lowRISC/mocha’s past year of commit activity
    SystemVerilog 23 9 130 13 Updated Mar 27, 2026
  • lowrisc-nix Public

    lowRISC Nix Packages and Environments

    lowRISC/lowrisc-nix’s past year of commit activity
    Nix 8 MIT 11 1 2 Updated Mar 24, 2026
  • opentitan-provisioning Public

    Reference OpenTitan Provisioning Infrastructure

    lowRISC/opentitan-provisioning’s past year of commit activity
    Go 14 Apache-2.0 10 17 2 Updated Mar 17, 2026
  • sonata-software Public

    Software, build flows and examples for the Sonata System

    lowRISC/sonata-software’s past year of commit activity
    C++ 13 Apache-2.0 17 4 0 Updated Mar 17, 2026
  • sonata-system Public

    A full micro-controller system utilizing the CHERIoT Ibex core, part of the Sunburst project funded by UKRI

    lowRISC/sonata-system’s past year of commit activity
    C++ 50 Apache-2.0 32 14 9 Updated Mar 16, 2026
  • riscv-isa-sim Public Forked from riscv-software-src/riscv-isa-sim

    RISC-V Functional ISA Simulator

    lowRISC/riscv-isa-sim’s past year of commit activity
    C 20 1,060 0 2 Updated Mar 16, 2026
  • sail-cheri-riscv Public Forked from CTSRD-CHERI/sail-cheri-riscv

    CHERI-RISC-V model written in Sail

    lowRISC/sail-cheri-riscv’s past year of commit activity
    Isabelle 0 25 0 0 Updated Feb 27, 2026
  • sail-riscv Public Forked from riscv/sail-riscv

    Sail RISC-V model

    lowRISC/sail-riscv’s past year of commit activity
    Coq 0 257 0 0 Updated Feb 27, 2026
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