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3516cv300 gpio0_2 without pinmux address #140

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a6897cc
Update tools.c
sansarus Feb 20, 2026
101148d
Update reginfo.c
sansarus Feb 20, 2026
cba4e8c
Update tools.c
sansarus Feb 20, 2026
110819b
Update tools.c
sansarus Feb 20, 2026
37f134a
Update reginfo.c
sansarus Feb 20, 2026
91049aa
Update reginfo.c
sansarus Feb 20, 2026
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3 changes: 2 additions & 1 deletion src/reginfo.c
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Original file line number Diff line number Diff line change
Expand Up @@ -801,6 +801,7 @@ MUXCTRL(CV300_muxctrl_reg62, 0x120400F8, "GPIO0_1", "TEMPER_DQ")
MUXCTRL(CV300_muxctrl_reg63, 0x120400FC, "GPIO8_0", "SAR_ADC_CH0")
MUXCTRL(CV300_muxctrl_reg64, 0x12040100, "GPIO8_1", "SAR_ADC_CH1")
MUXCTRL(CV300_muxctrl_reg65, 0x12040104, "GPIO8_2", "SAR_ADC_CH2")
MUXCTRL(CV300_muxctrl_reg66, 0xdeadbeef, "GPIO0_2")

static const muxctrl_reg_t *CV300regs[] = {
&CV300_muxctrl_reg0, &CV300_muxctrl_reg1, &CV300_muxctrl_reg2,
Expand All @@ -824,7 +825,7 @@ static const muxctrl_reg_t *CV300regs[] = {
&CV300_muxctrl_reg55, &CV300_muxctrl_reg56, &CV300_muxctrl_reg57,
&CV300_muxctrl_reg58, &CV300_muxctrl_reg59, &CV300_muxctrl_reg60,
&CV300_muxctrl_reg61, &CV300_muxctrl_reg62, &CV300_muxctrl_reg63,
&CV300_muxctrl_reg64, &CV300_muxctrl_reg65, 0,
&CV300_muxctrl_reg64, &CV300_muxctrl_reg65, &CV300_muxctrl_reg66, 0,
};

MUXCTRL(CV500_iocfg_reg0, 0x10FF0000, "EMMC_CLK", "SFC_CLK", "SFC_BOOT_MODE")
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7 changes: 7 additions & 0 deletions src/tools.c
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,13 @@ bool mem_reg(uint32_t addr, uint32_t *data, enum REG_OPS op) {
static uint32_t loaded_offset;
static uint32_t loaded_size;

// do nothing if no pinmux for this GPIO
if (addr == 0xdeadbeef) {
if (op == OP_READ)
*data = 0; //
return true;
}

uint32_t offset = addr & 0xffff0000;
uint32_t size = 0xffff;
if (!addr || (loaded_area && offset != loaded_offset)) {
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